It has been proven that quiescent supply current (I.sub.DDQ) monitoring is a suitable test technique which can be used as well for the verification of electronic devices or circuits as well as to increase the test quality of said devices or circuits. Especially in function of improved test quality an accurate supply current measurement system is needed.
Among functional, stuck-at, stuck-open, and Quiescent current test strategies, no single test method guarantees detection of all types of defects in electronic devices. As types of defects in electronic devices, a number of defects occurring in digital CMOS devices can be mentioned, such as gate-oxide shorts, bridges and floating gates. Such defects are not detected by a conventional voltage based test approach. Many defects that pose reliability risks are detected only by I.sub.DDQ testing, therefore multiple and accurate I.sub.DDQ tests are necessary for CMOS devices or IC's. The I.sub.DDQ test is the most sensitive and comprehensive strategy, but is a relatively slow measurement technique. The Quiescent current testing technique is based upon the fact that defective devices produce an abnormally high value of power supply current (I.sub.DD). The technique has been proven to be very efficient in detecting certain defects occurring in CMOS devices or IC's, requiring only a reduced number of test patterns.
The overall test cost of a circuit depends on the test pattern generation time, the fault coverage required, tester time for each unit of the circuit, and the number of circuits under test. While current test generation takes much less CPU time and generates fewer test patterns, testing a circuit using current tests (applied at kHz rates) requires more time than using logic tests (applied at MHz rates). Measuring the I.sub.DDQ current off-chip using a test monitor that is not on one chip with the electronic circuit or device that is tested causes difficulties for testing hardware and significantly decreases the test rate if standard measurement equipment, such as the Parametric Measurement Unit (PMU), is used. Basically two solutions to this problem exist. Using an on-chip monitor, integrated on one chip with the integrated circuit that is tested, can increase the test rate significantly. The alternative is to use a dedicated off-chip monitor. Nevertheless most I.sub.DDQ measurements in production testing nowadays are still done with off-chip instrumentation. A few experimental on-chip/off-chip current monitors have been proposed so far. One of them is already used in production testing.
To be able to perform I.sub.DDQ testing in an economical justified way, a dedicated measurement unit is needed. As on-chip built-in current monitors can achieve much higher testing speeds than off-chip alternatives, they have been evaluated as an appropriate choice for CMOS VLSI current testing.
Problem Definition
To measure accurately the quiescent supply current of the electronic circuit or Device Under Test (DUT), the measuring device should not influence the DUT's supply voltage and current in any condition, and be capable of driving the parasitic capacitance resulting from the DUT's supply wiring and decoupling capacitance. Most of the Built-in current monitors (BICs) presented so far are either intended to be inserted into the ground connection or leave the DUT's supply floating during measuring. By inserting a measuring device in the ground connection, a virtual ground for the devices under test is created, which when a current is flowing differs from the actual ground and thus affects the measurement accuracy.
The use of the Parametric Measurement Unit (PMU) available on a test system in a force voltage measure current mode offers a quantitative and accurate measurement. However the PMU is rather slow--measurement periods typically being 100 ms--and is not able to deliver switching spikes greater than 100 mA. As an example of such a device the PMU available on the Credence VISTAvision test system can be taken.
A monitor circuit called IDUNA, and disclosed in EP-0386804 was originally designed to serve as an on-chip monitor but can also be used as an off-chip monitor. The IDUNA generates a pass/fail decision based on an integrated comparison of the I.sub.DDQ against a scaled reference current. The advantage of the circuit is that its possible to reach high measuring speeds, improved accuracy and noise immunity. The monitor is designed to operate at frequencies above 1 MHz. Despite its advantages however, the IDUNA is not capable of driving high capacitive loads. It cannot deliver high transient currents and requires a complex characterisation and calibration procedure as its measurement characteristic is non linear. The IDUNA is intended to perform an accurate comparison of the measured quiescent current against a predefined reference current level rather than to perform an accurate current measurement of the quiescent current within a certain measurement range. Furthermore, due to its limited current delivering capability and limited capacitive load driving capability the IDUNA can only be used to test small circuits, and requires circuit partitioning in combination with the use of multiple monitors when on-chip current monitoring of bigger circuits is desired.
The OCIMU circuit, as disclosed in EP-0672911 is an off-chip monitor that is realised using discrete components. The OCIMU is capable of performing a relatively high speed (measurement time about 100 .mu.s for a 2 .mu.F load) current measurement especially when driving a high capacitive load (up to several .mu.F). This property is important as modern complex ASICs usually have multiple supply pins (sometimes more than 20). To assure a high quality stable supply on the chip a 100 nF decoupling capacitance is added to each of these supply pins. So a total decoupling capacitance of 2 .mu.F or more is not uncommon. The OCIMU circuit is also able to deliver transient currents of up to 10 amperes. This is necessary as telecommunication ASICs can demand switching currents in excess of 5 amperes, whereas the normal quiescent currents drawn range from 0.1 to 100 .mu.A. Furthermore the circuit requires only a minimum of easily performed calibration and delivers a well-regulated supply voltage to the DUT never leaving the DUT supply pin(s) floating. Another quality of the OCIMU is that this circuit attacks the problem of measuring the quiescent current in a hierarchical way. The circuit is designed such that first the order of magnitude of the I.sub.DDQ is determined, then only if the current is below a presettable level then an accurate measurement is performed. Otherwise the circuit is directly identified as a `bad part`, allowing the testing procedure to be speeded up. The drawbacks of the OCIMU circuit are that it can only serve as an off-chip monitor--as it cannot be easily integrated using a standard CMOS process due to its architectural concept--, that its testing speed is limited if current measurements with an accuracy of 1 .mu.A or better are desired--mainly due to the noise generated by its building blocks--, and that the circuit is highly sensible to noise present on the DUT's supply reference terminal--a high quality supply is needed with a noise level less than 1 mV.sub.ptp to assure the monitor's measurement accuracy
Aims of the Invention
It is an aim of the present invention to disclose a test system for electronic circuits or devices which not only can serve for accurately measuring the quiescent supply current (I.sub.DDQ) drawn by a circuit or device and for deciding whether the circuit or device is good or bad, but also can be easily adapted in function of the application with respect to the desired measurement range and the measurement accuracy.
It is another aim of the present invention to disclose a basic I.sub.DD measurement system which can be used for as well on-chip built-in current monitoring as for off-chip current monitoring in a broad range of applications.
It is a further aim of the present invention to disclose a test system that can be used for engineering as well as production testing which does not affect the supply voltage of the devices or circuits under test, which provides high speed and high accurate measurements, which can be easily integrated in a standard CMOS process, which overcomes the partitioning problem associated with other built-in current monitors and which can be easily adapted in function of the application with respect to the desired measurement range and accuracy. The I.sub.DD monitor of the present invention achieves these goals and can be used either as an off-chip or as an on-chip built-in current monitor, in both cases providing improved characteristics in comparison to other measurement devices.